Model a chip's cooling stack as a series thermal-resistance network, the same lumped approach used for a first-pass electronics thermal design.
Two rate equations, one common form. A conduction layer (TIM, spreader) follows Fourier's law, giving a thermal resistance of R = t / (k·A): thickness over conductivity times area. Heat leaving the heatsink into the surrounding air or liquid follows Newton's law of cooling, q = h·A·(Ts − T∞), which gives an equivalent thermal resistance of R = 1 / (h·A). Here h is the convection heat transfer coefficient (W/m²·K), a property of the fluid motion and thermophysical properties near the surface, and A is the effective surface area exposed to the fluid, including fins. Typical h: ~5–25 W/m²·K for free (natural) convection in air, ~25–100 W/m²·K for forced convection in air, and 1,000+ W/m²·K for convection in liquids. Any stage can also be set to a fixed Direct R if the value is already known from a datasheet or measurement.
Thermal Circuit Diagram: heat flow animates left to right
ColdHot
Chip & Limits
Total Resistance
0°C/W
Junction Temp
0°C
Margin to T_j,max
0°C
OK
Max Sustainable Power
0W
Stack Configuration
Model Assumptions & Limits
• 1-D, steady-state, series network. This is the quick lumped-resistance approach used for a first-pass sizing check before full CFD/FEA. It assumes uniform cross-sections through each conduction layer and a single heat path from junction to ambient.
• Radiation is neglected. This matters more for natural convection than for fan or liquid cooling. A typical radiative coefficient for a moderately warm, non-bare surface (h_rad ≈ 4–8 W/m²·K) is comparable in size to the h ≈ 10 W/m²·K used for the natural-convection preset here, so ignoring it can overstate natural-convection R (and T_j) by roughly 30–50%. For fan-forced air or liquid cooling, convection dominates by an order of magnitude or more and radiation is genuinely negligible.
• Spreading resistance is not modeled. Heat entering a spreader over a smaller area than the spreader's footprint incurs extra resistance beyond simple R = t/(k·A); this tool assumes heat is already uniformly distributed across each layer's stated area.
• The amber-outlined stage is your current bottleneck: the largest single contributor to total resistance, and the first place to focus to reduce junction temperature.